Resovling the opencv 4.10.0 compilation failure issue
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172
0193-Correct-shll-shll2-patterns.patch
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172
0193-Correct-shll-shll2-patterns.patch
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From 828cc9e3083f399ca550ba9617b20fc282a73896 Mon Sep 17 00:00:00 2001
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From: Diachkov Ilia <diachkov.ilia1@huawei-partners.com>
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Date: Thu, 29 Aug 2024 19:41:23 +0800
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Subject: [PATCH] Correct shll/shll2 patterns
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---
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gcc/config/aarch64/aarch64-simd.md | 34 +++++-----
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gcc/config/aarch64/predicates.md | 14 +++-
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gcc/testsuite/gcc.target/aarch64/jdcolor_le.c | 68 +++++++++++++++++++
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3 files changed, 98 insertions(+), 18 deletions(-)
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create mode 100644 gcc/testsuite/gcc.target/aarch64/jdcolor_le.c
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diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
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index 754343abc..523423784 100644
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--- a/gcc/config/aarch64/aarch64-simd.md
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+++ b/gcc/config/aarch64/aarch64-simd.md
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@@ -4712,16 +4712,16 @@
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[(set_attr "type" "neon_shift_imm_long")]
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)
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-(define_insn "*aarch64_simd_vec_unpacks_lo_shiftsi"
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- [(set (match_operand:V4SI 0 "register_operand" "=w")
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- (ashift:V4SI
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- (sign_extend:V4SI
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- (vec_select:V4HI
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- (match_operand:V8HI 1 "register_operand" "w")
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- (match_operand:V8HI 2 "vect_par_cnst_lo_half" "")))
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- (match_operand:V4SI 3 "aarch64_simd_shift_imm_bitsize_v4si" "i")))]
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+(define_insn "*aarch64_simd_vec_unpacks_lo_shift<mode>"
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+ [(set (match_operand:<VDBLW> 0 "register_operand" "=w")
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+ (ashift:<VDBLW>
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+ (sign_extend:<VDBLW>
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+ (vec_select:<VHALF>
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+ (match_operand:VQW 1 "register_operand" "w")
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+ (match_operand:VQW 2 "vect_par_cnst_lo_half" "")))
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+ (match_operand:<VDBLW> 3 "aarch64_simd_shift_imm_bitsize_<mode>" "i")))]
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"TARGET_SIMD"
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- "shll\t%0.4s, %1.4h, #%3"
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+ "shll\t%0.<Vwtype>, %1.<Vhalftype>, #%3"
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[(set_attr "type" "neon_shift_imm_long")]
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)
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@@ -4743,15 +4743,15 @@
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)
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(define_insn "*aarch64_simd_vec_unpacks_hi_shiftsi"
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- [(set (match_operand:V4SI 0 "register_operand" "=w")
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- (ashift:V4SI
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- (sign_extend:V4SI
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- (vec_select:V4HI
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- (match_operand:V8HI 1 "register_operand" "w")
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- (match_operand:V8HI 2 "vect_par_cnst_hi_half" "")))
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- (match_operand:V4SI 3 "aarch64_simd_shift_imm_bitsize_v4si" "i")))]
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+ [(set (match_operand:<VDBLW> 0 "register_operand" "=w")
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+ (ashift:<VDBLW>
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+ (sign_extend:<VDBLW>
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+ (vec_select:<VHALF>
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+ (match_operand:VQW 1 "register_operand" "w")
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+ (match_operand:VQW 2 "vect_par_cnst_hi_half" "")))
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+ (match_operand:<VDBLW> 3 "aarch64_simd_shift_imm_bitsize_<mode>" "i")))]
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"TARGET_SIMD"
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- "shll2\t%0.4s, %1.8h, #%3"
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+ "shll2\t%0.<Vwtype>, %1.<Vtype>, #%3"
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[(set_attr "type" "neon_shift_imm_long")]
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)
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diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
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index d0a55b44a..72c7ece57 100644
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--- a/gcc/config/aarch64/predicates.md
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+++ b/gcc/config/aarch64/predicates.md
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@@ -617,11 +617,23 @@
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(and (match_code "const_int")
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(match_test "IN_RANGE (INTVAL (op), 0, 64)")))
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+(define_predicate "aarch64_simd_shift_imm_bitsize_v16qi"
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+ (match_code "const_vector")
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+{
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+ return INTVAL (unwrap_const_vec_duplicate (op)) == 8;
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+})
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+
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+(define_predicate "aarch64_simd_shift_imm_bitsize_v8hi"
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+ (match_code "const_vector")
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+{
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+ return INTVAL (unwrap_const_vec_duplicate (op)) == 16;
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+})
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+
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(define_predicate "aarch64_simd_shift_imm_bitsize_v4si"
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(match_code "const_vector")
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{
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HOST_WIDE_INT val = INTVAL (unwrap_const_vec_duplicate (op));
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- return val == 8 || val == 16 || val == 32;
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+ return INTVAL (unwrap_const_vec_duplicate (op)) == 32;
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})
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(define_predicate "aarch64_constant_pool_symref"
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diff --git a/gcc/testsuite/gcc.target/aarch64/jdcolor_le.c b/gcc/testsuite/gcc.target/aarch64/jdcolor_le.c
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new file mode 100644
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index 000000000..2b66b13c1
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/aarch64/jdcolor_le.c
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@@ -0,0 +1,68 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O3" } */
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+/* It's a preprocessed part of libjpeg-turbo. */
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+
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+typedef int boolean;
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+typedef short INT16;
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+typedef unsigned short UINT16;
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+typedef long unsigned int size_t;
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+typedef long JLONG;
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+typedef unsigned int JDIMENSION;
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+typedef short J12SAMPLE;
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+typedef J12SAMPLE *J12SAMPROW;
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+typedef J12SAMPROW *J12SAMPARRAY;
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+typedef J12SAMPARRAY *J12SAMPIMAGE;
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+
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+void
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+rgb_rgb565_convert_le(JDIMENSION num_cols, J12SAMPIMAGE input_buf,
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+ JDIMENSION input_row, J12SAMPARRAY output_buf,
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+ int num_rows)
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+{
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+ register J12SAMPROW outptr;
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+ register J12SAMPROW inptr0, inptr1, inptr2;
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+ register JDIMENSION col;
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+
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+
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+ while (--num_rows >= 0) {
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+ JLONG rgb;
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+ unsigned int r, g, b;
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+
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+ inptr0 = input_buf[0][input_row];
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+ inptr1 = input_buf[1][input_row];
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+ inptr2 = input_buf[2][input_row];
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+ input_row++;
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+ outptr = *output_buf++;
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+ if ((((size_t)(outptr)) & 3)) {
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+ r = *inptr0++;
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+ g = *inptr1++;
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+ b = *inptr2++;
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+ rgb = ((((r) << 8) & 0xF800) | (((g) << 3) & 0x7E0) | ((b) >> 3));
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+ *(INT16 *)outptr = (INT16)rgb;
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+ outptr += 2;
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+ num_cols--;
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+ }
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+ for (col = 0; col < (num_cols >> 1); col++) {
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+ r = *inptr0++;
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+ g = *inptr1++;
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+ b = *inptr2++;
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+ rgb = ((((r) << 8) & 0xF800) | (((g) << 3) & 0x7E0) | ((b) >> 3));
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+
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+ r = *inptr0++;
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+ g = *inptr1++;
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+ b = *inptr2++;
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+ rgb = ((((((r) << 8) & 0xF800) | (((g) << 3) & 0x7E0) | ((b) >> 3)) << 16) | rgb);
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+
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+ ((*(int *)(outptr)) = rgb);
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+ outptr += 4;
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+ }
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+ if (num_cols & 1) {
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+ r = *inptr0;
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+ g = *inptr1;
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+ b = *inptr2;
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+ rgb = ((((r) << 8) & 0xF800) | (((g) << 3) & 0x7E0) | ((b) >> 3));
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+ *(INT16 *)outptr = (INT16)rgb;
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+ }
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+ }
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+}
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+/* We should not generate shll[2] for this test case. */
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+/* { dg-final { scan-assembler-not "shll" } } */
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--
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2.19.1
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10
gcc.spec
10
gcc.spec
@ -61,7 +61,7 @@
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Summary: Various compilers (C, C++, Objective-C, ...)
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Name: gcc
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Version: %{gcc_version}
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Release: 56
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Release: 57
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License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ with exceptions and LGPLv2+ and BSD
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URL: https://gcc.gnu.org
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@ -300,6 +300,7 @@ Patch189: 0189-Add-hip11-CPU-pipeline-scheduling.patch
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Patch190: 0190-Strcut-Reorg-fix-spec2017-505-build-issue-with-fipa-.patch
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Patch191: 0191-Revert-feature-mull64.patch
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Patch192: 0192-Fix-fail-in-cmtst-patterns-src-openEuler-gcc-IA52SK.patch
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Patch193: 0193-Correct-shll-shll2-patterns.patch
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%global gcc_target_platform %{_arch}-linux-gnu
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@ -945,6 +946,7 @@ not stable, so plugins must be rebuilt any time GCC is updated.
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%patch190 -p1
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%patch191 -p1
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%patch192 -p1
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%patch193 -p1
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%build
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@ -2974,6 +2976,12 @@ end
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%doc rpm.doc/changelogs/libcc1/ChangeLog*
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%changelog
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* Tue Jan 21 2025 M-jiang <2910392225@qq.com> - 10.3.1-57
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- Type:Bugfix
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- ID:NA
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- SUG:NA
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- DESC:Correct shll/shll2 patterns
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* Fri Jan 17 2025 huzife <634763349@qq.com> - 10.3.1-56
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- Type:Bugfix
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- ID:NA
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