58 lines
2.2 KiB
Diff
58 lines
2.2 KiB
Diff
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From ea8049e63b663cab607d1f900ce593547485b33b Mon Sep 17 00:00:00 2001
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From: zhujun2 <zhujun2_yewu@cmss.chinamobile.com>
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Date: Wed, 10 Apr 2024 20:02:38 -0700
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Subject: [PATCH] amd_iommu: Fix APIC address check
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An MSI from I/O APIC may not exactly equal to APIC_DEFAULT_ADDRESS. In
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fact, Windows 17763.3650 configures I/O APIC to set the dest_mode bit.
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Cover the range assigned to APIC.
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Fixes: 577c470f43 ("x86_iommu/amd: Prepare for interrupt remap support")
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Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
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Message-Id: <20230921114612.40671-1-akihiko.odaki@daynix.com>
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Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
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Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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(cherry picked from commit 0114c4513095598cdf1cd8d7dacdfff757628121)
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Signed-off-by: zhujun2 <zhujun2_yewu@cmss.chinamobile.com>
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---
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hw/i386/amd_iommu.c | 9 ++-------
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hw/i386/amd_iommu.h | 2 --
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2 files changed, 2 insertions(+), 9 deletions(-)
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diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
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index 4d13d8e697..dfb9a2d8e6 100644
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--- a/hw/i386/amd_iommu.c
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+++ b/hw/i386/amd_iommu.c
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@@ -1245,13 +1245,8 @@ static int amdvi_int_remap_msi(AMDVIState *iommu,
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return -AMDVI_IR_ERR;
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}
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- if (origin->address & AMDVI_MSI_ADDR_HI_MASK) {
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- trace_amdvi_err("MSI address high 32 bits non-zero when "
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- "Interrupt Remapping enabled.");
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- return -AMDVI_IR_ERR;
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- }
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-
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- if ((origin->address & AMDVI_MSI_ADDR_LO_MASK) != APIC_DEFAULT_ADDRESS) {
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+ if (origin->address < AMDVI_INT_ADDR_FIRST ||
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+ origin->address + sizeof(origin->data) > AMDVI_INT_ADDR_LAST + 1) {
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trace_amdvi_err("MSI is not from IOAPIC.");
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return -AMDVI_IR_ERR;
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}
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diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h
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index 79d38a3e41..210a37dfb1 100644
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--- a/hw/i386/amd_iommu.h
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+++ b/hw/i386/amd_iommu.h
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@@ -210,8 +210,6 @@
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#define AMDVI_INT_ADDR_FIRST 0xfee00000
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#define AMDVI_INT_ADDR_LAST 0xfeefffff
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#define AMDVI_INT_ADDR_SIZE (AMDVI_INT_ADDR_LAST - AMDVI_INT_ADDR_FIRST + 1)
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-#define AMDVI_MSI_ADDR_HI_MASK (0xffffffff00000000ULL)
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-#define AMDVI_MSI_ADDR_LO_MASK (0x00000000ffffffffULL)
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/* SB IOAPIC is always on this device in AMD systems */
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#define AMDVI_IOAPIC_SB_DEVID PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
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--
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2.27.0
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