63 lines
2.4 KiB
Diff
63 lines
2.4 KiB
Diff
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From 1a52d742851a68772aeb1d6d18bb57e58d78b2d2 Mon Sep 17 00:00:00 2001
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From: guping <guping_yewu@cmss.chinamobile.com>
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Date: Tue, 25 Jun 2024 11:33:54 +0000
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Subject: [PATCH] hw/intc/arm_gic: Fix deactivation of SPI lines chery-pick
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from 7175a562f157d39725ab396e39c1e8e410d206b3
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Julien reported that he has seen strange behaviour when running
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Xen on QEMU using GICv2. When Xen migrates a guest's vCPU from
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one pCPU to another while the vCPU is handling an interrupt, the
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guest is unable to properly deactivate interrupts.
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Looking at it a little closer, our GICv2 model treats
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deactivation of SPI lines as if they were PPI's, i.e banked per
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CPU core. The state for active interrupts should only be banked
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for PPI lines, not for SPI lines.
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Make deactivation of SPI lines unbanked, similar to how we
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handle writes to GICD_ICACTIVER.
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Reported-by: default avatarJulien Grall <julien@xen.org>
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Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@amd.com>
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Message-id: 20240605143044.2029444-2-edgar.iglesias@gmail.com
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Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
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Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
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Signed-off-by: guping <guping_yewu@cmss.chinamobile.com>
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---
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hw/intc/gic_internal.h | 8 ++++++--
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1 file changed, 6 insertions(+), 2 deletions(-)
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diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
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index 8d29b40ca1..8ddbf554c6 100644
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--- a/hw/intc/gic_internal.h
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+++ b/hw/intc/gic_internal.h
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@@ -280,6 +280,8 @@ static inline void gic_set_active(GICState *s, int irq, int cpu)
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static inline void gic_clear_active(GICState *s, int irq, int cpu)
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{
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+ unsigned int cm;
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+
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if (gic_is_vcpu(cpu)) {
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uint32_t *entry = gic_get_lr_entry(s, irq, cpu);
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GICH_LR_CLEAR_ACTIVE(*entry);
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@@ -301,11 +303,13 @@ static inline void gic_clear_active(GICState *s, int irq, int cpu)
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* the GIC is secure.
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*/
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if (!s->security_extn || GIC_DIST_TEST_GROUP(phys_irq, 1 << rcpu)) {
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- GIC_DIST_CLEAR_ACTIVE(phys_irq, 1 << rcpu);
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+ cm = phys_irq < GIC_INTERNAL ? 1 << rcpu : ALL_CPU_MASK;
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+ GIC_DIST_CLEAR_ACTIVE(phys_irq, cm);
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}
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}
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} else {
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- GIC_DIST_CLEAR_ACTIVE(irq, 1 << cpu);
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+ cm = irq < GIC_INTERNAL ? 1 << cpu : ALL_CPU_MASK;
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+ GIC_DIST_CLEAR_ACTIVE(irq, cm);
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}
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}
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--
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2.41.0.windows.1
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