119 lines
4.6 KiB
Diff
119 lines
4.6 KiB
Diff
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From c006e700cf6f1925dc9400d37e2e6c9c53b7bc92 Mon Sep 17 00:00:00 2001
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From: Babu Moger <babu.moger@amd.com>
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Date: Thu, 4 May 2023 15:53:09 -0500
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Subject: [PATCH] target/i386: Add feature bits for CPUID_Fn80000021_EAX
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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mainline inclusion
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from mainline-8.1.0
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commit b70eec312b185197d639bff689007727e596afd1
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category: feature
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bugzilla: https://gitee.com/openeuler/qemu/issues/IAUSKJ
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Reference: https://gitlab.com/qemu-project/qemu/-/commit/b70eec312b185197d639bff689007727e596afd1
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commit b70eec312b185197d639bff689007727e596afd1 upstream
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Add the following feature bits.
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no-nested-data-bp : Processor ignores nested data breakpoints.
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lfence-always-serializing : LFENCE instruction is always serializing.
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null-sel-cls-base : Null Selector Clears Base. When this bit is
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set, a null segment load clears the segment base.
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The documentation for the features are available in the links below.
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a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
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Revision B1 Processors
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b. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision
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40332 4.05 Date October 2022
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Signed-off-by: Babu Moger <babu.moger@amd.com>
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Acked-by: Michael S. Tsirkin <mst@redhat.com>
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Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
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Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf
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Message-Id: <20230504205313.225073-5-babu.moger@amd.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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---
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target/i386/cpu.c | 24 ++++++++++++++++++++++++
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target/i386/cpu.h | 8 ++++++++
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2 files changed, 32 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 02d19c2b4e..527135ca9d 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -958,6 +958,22 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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.tcg_features = 0,
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.unmigratable_flags = 0,
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},
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+ [FEAT_8000_0021_EAX] = {
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+ .type = CPUID_FEATURE_WORD,
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+ .feat_names = {
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+ "no-nested-data-bp", NULL, "lfence-always-serializing", NULL,
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+ NULL, NULL, "null-sel-clr-base", NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ },
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+ .cpuid = { .eax = 0x80000021, .reg = R_EAX, },
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+ .tcg_features = 0,
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+ .unmigratable_flags = 0,
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+ },
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[FEAT_XSAVE] = {
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.type = CPUID_FEATURE_WORD,
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.feat_names = {
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@@ -6542,6 +6558,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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*ebx |= sev_get_reduced_phys_bits() << 6;
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}
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break;
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+ case 0x80000021:
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+ *eax = env->features[FEAT_8000_0021_EAX];
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+ *ebx = *ecx = *edx = 0;
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+ break;
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default:
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/* reserved values: zero */
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*eax = 0;
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@@ -6949,6 +6969,10 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
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x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
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}
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+ if (env->features[FEAT_8000_0021_EAX]) {
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+ x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021);
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+ }
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+
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/* SGX requires CPUID[0x12] for EPC enumeration */
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if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) {
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x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12);
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 623bd0e4d6..7b1190c3f2 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -585,6 +585,7 @@ typedef enum FeatureWord {
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FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
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FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
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FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */
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+ FEAT_8000_0021_EAX, /* CPUID[8000_0021].EAX */
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FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
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FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
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FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */
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@@ -941,6 +942,13 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
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/* Predictive Store Forwarding Disable */
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#define CPUID_8000_0008_EBX_AMD_PSFD (1U << 28)
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+/* Processor ignores nested data breakpoints */
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+#define CPUID_8000_0021_EAX_No_NESTED_DATA_BP (1U << 0)
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+/* LFENCE is always serializing */
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+#define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2)
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+/* Null Selector Clears Base */
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+#define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6)
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+
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#define CPUID_XSAVE_XSAVEOPT (1U << 0)
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#define CPUID_XSAVE_XSAVEC (1U << 1)
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#define CPUID_XSAVE_XGETBV1 (1U << 2)
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--
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2.45.1.windows.1
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