85 lines
4.1 KiB
Diff
85 lines
4.1 KiB
Diff
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From 05cee5f46432c4eb9774b53d014c5799bd924b8d Mon Sep 17 00:00:00 2001
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From: Liu Jing <liujing_yewu@cmss.chinamobile.com>
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Date: Mon, 14 Oct 2024 15:54:33 +0800
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Subject: [PATCH] target/ppc: Set result to QNaN for DENBCD when VXCVI occurs
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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According to the ISA, for instruction DENBCD:
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"If an invalid BCD digit or sign code is detected in the source
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operand, an invalid-operation exception (VXCVI) occurs."
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In the Invalid Operation Exception section, there is the situation:
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"When Invalid Operation Exception is disabled (VE=0) and Invalid
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Operation occurs (...) If the operation is an (...) or format the
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target FPR is set to a Quiet NaN". This was not being done in
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QEMU.
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This patch sets the result to QNaN when the instruction DENBCD causes
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an Invalid Operation Exception.
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Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
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Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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Message-Id: <20220906125523.38765-5-victor.colombo@eldorado.org.br>
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Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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Signed-off-by: Liu Jing <liujing_yewu@cmss.chinamobile.com>
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---
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target/ppc/dfp_helper.c | 26 ++++++++++++++++++++++++--
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1 file changed, 24 insertions(+), 2 deletions(-)
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diff --git a/target/ppc/dfp_helper.c b/target/ppc/dfp_helper.c
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index 0d01ac3de0..0398b3a50e 100644
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--- a/target/ppc/dfp_helper.c
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+++ b/target/ppc/dfp_helper.c
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@@ -1144,6 +1144,26 @@ static inline uint8_t dfp_get_bcd_digit_128(ppc_vsr_t *t, unsigned n)
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return t->VsrD((n & 0x10) ? 0 : 1) >> ((n << 2) & 63) & 15;
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}
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+static inline void dfp_invalid_op_vxcvi_64(struct PPC_DFP *dfp)
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+{
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+ /* TODO: fpscr is incorrectly not being saved to env */
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+ dfp_set_FPSCR_flag(dfp, FP_VX | FP_VXCVI, FPSCR_VE);
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+ if ((dfp->env->fpscr & FP_VE) == 0) {
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+ dfp->vt.VsrD(1) = 0x7c00000000000000; /* QNaN */
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+ }
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+}
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+
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+
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+static inline void dfp_invalid_op_vxcvi_128(struct PPC_DFP *dfp)
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+{
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+ /* TODO: fpscr is incorrectly not being saved to env */
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+ dfp_set_FPSCR_flag(dfp, FP_VX | FP_VXCVI, FPSCR_VE);
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+ if ((dfp->env->fpscr & FP_VE) == 0) {
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+ dfp->vt.VsrD(0) = 0x7c00000000000000; /* QNaN */
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+ dfp->vt.VsrD(1) = 0x0;
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+ }
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+}
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+
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#define DFP_HELPER_ENBCD(op, size) \
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void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b, \
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uint32_t s) \
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@@ -1170,7 +1190,8 @@ void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b, \
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sgn = 0; \
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break; \
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default: \
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- dfp_set_FPSCR_flag(&dfp, FP_VX | FP_VXCVI, FPSCR_VE); \
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+ dfp_invalid_op_vxcvi_##size(&dfp); \
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+ set_dfp##size(t, &dfp.vt); \
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return; \
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} \
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} \
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@@ -1180,7 +1201,8 @@ void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b, \
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digits[(size) / 4 - n] = dfp_get_bcd_digit_##size(&dfp.vb, \
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offset++); \
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if (digits[(size) / 4 - n] > 10) { \
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- dfp_set_FPSCR_flag(&dfp, FP_VX | FP_VXCVI, FPSCR_VE); \
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+ dfp_invalid_op_vxcvi_##size(&dfp); \
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+ set_dfp##size(t, &dfp.vt); \
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return; \
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} else { \
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nonzero |= (digits[(size) / 4 - n] > 0); \
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--
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2.41.0.windows.1
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