From 0a0923bb4835623af902f414e77565f2eb77ef2f Mon Sep 17 00:00:00 2001 From: Jiabo Feng Date: Sat, 30 Nov 2024 09:11:21 +0800 Subject: [PATCH] QEMU update to version 6.2.0-102: - target/ppc: Remove unused xer_* macros - hw/mips: Build fw_cfg.c once - minikconf: print error entirely on stderr - target/ppc: Remove extra space from s128 field in ppc_vsr_t - hw/arm/virt:Keep Guest L1 cache type consistent with KVM - pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy synonym Signed-off-by: Jiabo Feng (cherry picked from commit d1b87187cf117c1b09ecb9422379af9a66c6f949) --- ...-Guest-L1-cache-type-consistent-with.patch | 669 ++++++++++++++++++ hw-mips-Build-fw_cfg.c-once.patch | 37 + ...kconf-print-error-entirely-on-stderr.patch | 38 + ...Use-the-official-xkb-name-for-Arabic.patch | 61 ++ qemu.spec | 16 +- ...e-extra-space-from-s128-field-in-ppc.patch | 37 + target-ppc-Remove-unused-xer_-macros.patch | 39 + 7 files changed, 896 insertions(+), 1 deletion(-) create mode 100644 hw-arm-virt-Keep-Guest-L1-cache-type-consistent-with.patch create mode 100644 hw-mips-Build-fw_cfg.c-once.patch create mode 100644 minikconf-print-error-entirely-on-stderr.patch create mode 100644 pc-bios-keymaps-Use-the-official-xkb-name-for-Arabic.patch create mode 100644 target-ppc-Remove-extra-space-from-s128-field-in-ppc.patch create mode 100644 target-ppc-Remove-unused-xer_-macros.patch diff --git a/hw-arm-virt-Keep-Guest-L1-cache-type-consistent-with.patch b/hw-arm-virt-Keep-Guest-L1-cache-type-consistent-with.patch new file mode 100644 index 0000000..9118589 --- /dev/null +++ b/hw-arm-virt-Keep-Guest-L1-cache-type-consistent-with.patch @@ -0,0 +1,669 @@ +From a898db34ae36f10a0d03c59b2ad57a6e990b10e7 Mon Sep 17 00:00:00 2001 +From: Jia Qingtong +Date: Tue, 24 Sep 2024 18:24:33 +0800 +Subject: [PATCH] hw/arm/virt:Keep Guest L1 cache type consistent with KVM + +Linux KVM normalize the cache configuration and expose a +fabricated CLIDR_EL1 value to guest, where L1 cache type +could be unified or seperate instruction cache and data +cache. Let's keep guest L1 cache type consistent with +KVM by checking the guest visable CLIDR_EL1, which can +avoid abnormal issue in guest when it's probing cache +info conbined CLIDR_EL1 with ACPI PPTT and DT. + +Signed-off-by: Yanan Wang +Signed-off-by: lishusen +--- + hw/acpi/aml-build.c | 165 ++--------------------------------- + hw/arm/virt-acpi-build.c | 167 ++++++++++++++++++++++++++++++++++++ + hw/arm/virt.c | 86 +++++++++++++++---- + include/hw/acpi/aml-build.h | 52 ++--------- + include/hw/arm/virt.h | 60 +++++++++++++ + 5 files changed, 306 insertions(+), 224 deletions(-) + +diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c +index 39b8d807c0..0a9981acc1 100644 +--- a/hw/acpi/aml-build.c ++++ b/hw/acpi/aml-build.c +@@ -47,7 +47,7 @@ static void build_prepend_byte(GArray *array, uint8_t val) + g_array_prepend_val(array, val); + } + +-static void build_append_byte(GArray *array, uint8_t val) ++void build_append_byte(GArray *array, uint8_t val) + { + g_array_append_val(array, val); + } +@@ -1990,10 +1990,10 @@ void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms, + * ACPI spec, Revision 6.3 + * 5.2.29.1 Processor hierarchy node structure (Type 0) + */ +-static void build_processor_hierarchy_node(GArray *tbl, uint32_t flags, +- uint32_t parent, uint32_t id, +- uint32_t *priv_rsrc, +- uint32_t priv_num) ++void build_processor_hierarchy_node(GArray *tbl, uint32_t flags, ++ uint32_t parent, uint32_t id, ++ uint32_t *priv_rsrc, ++ uint32_t priv_num) + { + int i; + +@@ -2016,161 +2016,6 @@ static void build_processor_hierarchy_node(GArray *tbl, uint32_t flags, + } + } + +-/* +- * ACPI spec, Revision 6.3 +- * 5.2.29.2 Cache Type Structure (Type 1) +- */ +-static void build_cache_hierarchy_node(GArray *tbl, uint32_t next_level, +- uint32_t cache_type) +-{ +- build_append_byte(tbl, 1); +- build_append_byte(tbl, 24); +- build_append_int_noprefix(tbl, 0, 2); +- build_append_int_noprefix(tbl, 127, 4); +- build_append_int_noprefix(tbl, next_level, 4); +- +- switch (cache_type) { +- case ARM_L1D_CACHE: /* L1 dcache info */ +- build_append_int_noprefix(tbl, ARM_L1DCACHE_SIZE, 4); +- build_append_int_noprefix(tbl, ARM_L1DCACHE_SETS, 4); +- build_append_byte(tbl, ARM_L1DCACHE_ASSOCIATIVITY); +- build_append_byte(tbl, ARM_L1DCACHE_ATTRIBUTES); +- build_append_int_noprefix(tbl, ARM_L1DCACHE_LINE_SIZE, 2); +- break; +- case ARM_L1I_CACHE: /* L1 icache info */ +- build_append_int_noprefix(tbl, ARM_L1ICACHE_SIZE, 4); +- build_append_int_noprefix(tbl, ARM_L1ICACHE_SETS, 4); +- build_append_byte(tbl, ARM_L1ICACHE_ASSOCIATIVITY); +- build_append_byte(tbl, ARM_L1ICACHE_ATTRIBUTES); +- build_append_int_noprefix(tbl, ARM_L1ICACHE_LINE_SIZE, 2); +- break; +- case ARM_L2_CACHE: /* L2 cache info */ +- build_append_int_noprefix(tbl, ARM_L2CACHE_SIZE, 4); +- build_append_int_noprefix(tbl, ARM_L2CACHE_SETS, 4); +- build_append_byte(tbl, ARM_L2CACHE_ASSOCIATIVITY); +- build_append_byte(tbl, ARM_L2CACHE_ATTRIBUTES); +- build_append_int_noprefix(tbl, ARM_L2CACHE_LINE_SIZE, 2); +- break; +- case ARM_L3_CACHE: /* L3 cache info */ +- build_append_int_noprefix(tbl, ARM_L3CACHE_SIZE, 4); +- build_append_int_noprefix(tbl, ARM_L3CACHE_SETS, 4); +- build_append_byte(tbl, ARM_L3CACHE_ASSOCIATIVITY); +- build_append_byte(tbl, ARM_L3CACHE_ATTRIBUTES); +- build_append_int_noprefix(tbl, ARM_L3CACHE_LINE_SIZE, 2); +- break; +- default: +- build_append_int_noprefix(tbl, 0, 4); +- build_append_int_noprefix(tbl, 0, 4); +- build_append_byte(tbl, 0); +- build_append_byte(tbl, 0); +- build_append_int_noprefix(tbl, 0, 2); +- } +-} +- +-/* +- * ACPI spec, Revision 6.3 +- * 5.2.29 Processor Properties Topology Table (PPTT) +- */ +-void build_pptt_arm(GArray *table_data, BIOSLinker *linker, MachineState *ms, +- const char *oem_id, const char *oem_table_id) +-{ +- MachineClass *mc = MACHINE_GET_CLASS(ms); +- GQueue *list = g_queue_new(); +- guint pptt_start = table_data->len; +- guint parent_offset; +- guint length, i; +- int uid = 0; +- int socket; +- AcpiTable table = { .sig = "PPTT", .rev = 2, +- .oem_id = oem_id, .oem_table_id = oem_table_id }; +- +- acpi_table_begin(&table, table_data); +- +- for (socket = 0; socket < ms->smp.sockets; socket++) { +- uint32_t l3_cache_offset = table_data->len - pptt_start; +- build_cache_hierarchy_node(table_data, 0, ARM_L3_CACHE); +- +- g_queue_push_tail(list, +- GUINT_TO_POINTER(table_data->len - pptt_start)); +- build_processor_hierarchy_node( +- table_data, +- /* +- * Physical package - represents the boundary +- * of a physical package +- */ +- (1 << 0), +- 0, socket, &l3_cache_offset, 1); +- } +- +- if (mc->smp_props.clusters_supported) { +- length = g_queue_get_length(list); +- for (i = 0; i < length; i++) { +- int cluster; +- +- parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); +- for (cluster = 0; cluster < ms->smp.clusters; cluster++) { +- g_queue_push_tail(list, +- GUINT_TO_POINTER(table_data->len - pptt_start)); +- build_processor_hierarchy_node( +- table_data, +- (0 << 0), /* not a physical package */ +- parent_offset, cluster, NULL, 0); +- } +- } +- } +- +- length = g_queue_get_length(list); +- for (i = 0; i < length; i++) { +- int core; +- +- parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); +- for (core = 0; core < ms->smp.cores; core++) { +- uint32_t priv_rsrc[3] = {}; +- priv_rsrc[0] = table_data->len - pptt_start; /* L2 cache offset */ +- build_cache_hierarchy_node(table_data, 0, ARM_L2_CACHE); +- +- priv_rsrc[1] = table_data->len - pptt_start; /* L1 dcache offset */ +- build_cache_hierarchy_node(table_data, priv_rsrc[0], ARM_L1D_CACHE); +- +- priv_rsrc[2] = table_data->len - pptt_start; /* L1 icache offset */ +- build_cache_hierarchy_node(table_data, priv_rsrc[0], ARM_L1I_CACHE); +- +- if (ms->smp.threads > 1) { +- g_queue_push_tail(list, +- GUINT_TO_POINTER(table_data->len - pptt_start)); +- build_processor_hierarchy_node( +- table_data, +- (0 << 0), /* not a physical package */ +- parent_offset, core, priv_rsrc, 3); +- } else { +- build_processor_hierarchy_node( +- table_data, +- (1 << 1) | /* ACPI Processor ID valid */ +- (1 << 3), /* Node is a Leaf */ +- parent_offset, uid++, priv_rsrc, 3); +- } +- } +- } +- +- length = g_queue_get_length(list); +- for (i = 0; i < length; i++) { +- int thread; +- +- parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); +- for (thread = 0; thread < ms->smp.threads; thread++) { +- build_processor_hierarchy_node( +- table_data, +- (1 << 1) | /* ACPI Processor ID valid */ +- (1 << 2) | /* Processor is a Thread */ +- (1 << 3), /* Node is a Leaf */ +- parent_offset, uid++, NULL, 0); +- } +- } +- +- g_queue_free(list); +- acpi_table_end(linker, &table); +-} +- + /* + * ACPI spec, Revision 6.3 + * 5.2.29 Processor Properties Topology Table (PPTT) +diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c +index 89cecdd8e6..ed220d5d40 100644 +--- a/hw/arm/virt-acpi-build.c ++++ b/hw/arm/virt-acpi-build.c +@@ -60,6 +60,173 @@ + + #define ACPI_BUILD_TABLE_SIZE 0x20000 + ++/* ++ * ACPI spec, Revision 6.3 ++ * 5.2.29.2 Cache Type Structure (Type 1) ++ */ ++static void build_cache_hierarchy_node(GArray *tbl, uint32_t next_level, ++ uint32_t cache_type) ++{ ++ build_append_byte(tbl, 1); ++ build_append_byte(tbl, 24); ++ build_append_int_noprefix(tbl, 0, 2); ++ build_append_int_noprefix(tbl, 127, 4); ++ build_append_int_noprefix(tbl, next_level, 4); ++ ++ switch (cache_type) { ++ case ARM_L1D_CACHE: /* L1 dcache info */ ++ build_append_int_noprefix(tbl, ARM_L1DCACHE_SIZE, 4); ++ build_append_int_noprefix(tbl, ARM_L1DCACHE_SETS, 4); ++ build_append_byte(tbl, ARM_L1DCACHE_ASSOCIATIVITY); ++ build_append_byte(tbl, ARM_L1DCACHE_ATTRIBUTES); ++ build_append_int_noprefix(tbl, ARM_L1DCACHE_LINE_SIZE, 2); ++ break; ++ case ARM_L1I_CACHE: /* L1 icache info */ ++ build_append_int_noprefix(tbl, ARM_L1ICACHE_SIZE, 4); ++ build_append_int_noprefix(tbl, ARM_L1ICACHE_SETS, 4); ++ build_append_byte(tbl, ARM_L1ICACHE_ASSOCIATIVITY); ++ build_append_byte(tbl, ARM_L1ICACHE_ATTRIBUTES); ++ build_append_int_noprefix(tbl, ARM_L1ICACHE_LINE_SIZE, 2); ++ break; ++ case ARM_L1_CACHE: /* L1 cache info */ ++ build_append_int_noprefix(tbl, ARM_L1CACHE_SIZE, 4); ++ build_append_int_noprefix(tbl, ARM_L1CACHE_SETS, 4); ++ build_append_byte(tbl, ARM_L1CACHE_ASSOCIATIVITY); ++ build_append_byte(tbl, ARM_L1CACHE_ATTRIBUTES); ++ build_append_int_noprefix(tbl, ARM_L1CACHE_LINE_SIZE, 2); ++ break; ++ case ARM_L2_CACHE: /* L2 cache info */ ++ build_append_int_noprefix(tbl, ARM_L2CACHE_SIZE, 4); ++ build_append_int_noprefix(tbl, ARM_L2CACHE_SETS, 4); ++ build_append_byte(tbl, ARM_L2CACHE_ASSOCIATIVITY); ++ build_append_byte(tbl, ARM_L2CACHE_ATTRIBUTES); ++ build_append_int_noprefix(tbl, ARM_L2CACHE_LINE_SIZE, 2); ++ break; ++ case ARM_L3_CACHE: /* L3 cache info */ ++ build_append_int_noprefix(tbl, ARM_L3CACHE_SIZE, 4); ++ build_append_int_noprefix(tbl, ARM_L3CACHE_SETS, 4); ++ build_append_byte(tbl, ARM_L3CACHE_ASSOCIATIVITY); ++ build_append_byte(tbl, ARM_L3CACHE_ATTRIBUTES); ++ build_append_int_noprefix(tbl, ARM_L3CACHE_LINE_SIZE, 2); ++ break; ++ default: ++ build_append_int_noprefix(tbl, 0, 4); ++ build_append_int_noprefix(tbl, 0, 4); ++ build_append_byte(tbl, 0); ++ build_append_byte(tbl, 0); ++ build_append_int_noprefix(tbl, 0, 2); ++ } ++} ++ ++/* ++ * ACPI spec, Revision 6.3 ++ * 5.2.29 Processor Properties Topology Table (PPTT) ++ */ ++static void build_pptt_arm(GArray *table_data, BIOSLinker *linker, MachineState *ms, ++ const char *oem_id, const char *oem_table_id) ++{ ++ MachineClass *mc = MACHINE_GET_CLASS(ms); ++ GQueue *list = g_queue_new(); ++ guint pptt_start = table_data->len; ++ guint parent_offset; ++ guint length, i; ++ int uid = 0; ++ int socket; ++ AcpiTable table = { .sig = "PPTT", .rev = 2, ++ .oem_id = oem_id, .oem_table_id = oem_table_id }; ++ bool unified_l1 = cpu_l1_cache_unified(0); ++ ++ acpi_table_begin(&table, table_data); ++ ++ for (socket = 0; socket < ms->smp.sockets; socket++) { ++ uint32_t l3_cache_offset = table_data->len - pptt_start; ++ build_cache_hierarchy_node(table_data, 0, ARM_L3_CACHE); ++ ++ g_queue_push_tail(list, ++ GUINT_TO_POINTER(table_data->len - pptt_start)); ++ build_processor_hierarchy_node( ++ table_data, ++ /* ++ * Physical package - represents the boundary ++ * of a physical package ++ */ ++ (1 << 0), ++ 0, socket, &l3_cache_offset, 1); ++ } ++ ++ if (mc->smp_props.clusters_supported) { ++ length = g_queue_get_length(list); ++ for (i = 0; i < length; i++) { ++ int cluster; ++ ++ parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); ++ for (cluster = 0; cluster < ms->smp.clusters; cluster++) { ++ g_queue_push_tail(list, ++ GUINT_TO_POINTER(table_data->len - pptt_start)); ++ build_processor_hierarchy_node( ++ table_data, ++ (0 << 0), /* not a physical package */ ++ parent_offset, cluster, NULL, 0); ++ } ++ } ++ } ++ ++ length = g_queue_get_length(list); ++ for (i = 0; i < length; i++) { ++ int core; ++ ++ parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); ++ for (core = 0; core < ms->smp.cores; core++) { ++ uint32_t priv_rsrc[3] = {}; ++ priv_rsrc[0] = table_data->len - pptt_start; /* L2 cache offset */ ++ build_cache_hierarchy_node(table_data, 0, ARM_L2_CACHE); ++ ++ if (unified_l1) { ++ priv_rsrc[1] = table_data->len - pptt_start; /* L1 cache offset */ ++ build_cache_hierarchy_node(table_data, priv_rsrc[0], ARM_L1_CACHE); ++ } else { ++ priv_rsrc[1] = table_data->len - pptt_start; /* L1 dcache offset */ ++ build_cache_hierarchy_node(table_data, priv_rsrc[0], ARM_L1D_CACHE); ++ priv_rsrc[2] = table_data->len - pptt_start; /* L1 icache offset */ ++ build_cache_hierarchy_node(table_data, priv_rsrc[0], ARM_L1I_CACHE); ++ } ++ ++ if (ms->smp.threads > 1) { ++ g_queue_push_tail(list, ++ GUINT_TO_POINTER(table_data->len - pptt_start)); ++ build_processor_hierarchy_node( ++ table_data, ++ (0 << 0), /* not a physical package */ ++ parent_offset, core, priv_rsrc, 3); ++ } else { ++ build_processor_hierarchy_node( ++ table_data, ++ (1 << 1) | /* ACPI Processor ID valid */ ++ (1 << 3), /* Node is a Leaf */ ++ parent_offset, uid++, priv_rsrc, 3); ++ } ++ } ++ } ++ ++ length = g_queue_get_length(list); ++ for (i = 0; i < length; i++) { ++ int thread; ++ ++ parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list)); ++ for (thread = 0; thread < ms->smp.threads; thread++) { ++ build_processor_hierarchy_node( ++ table_data, ++ (1 << 1) | /* ACPI Processor ID valid */ ++ (1 << 2) | /* Processor is a Thread */ ++ (1 << 3), /* Node is a Leaf */ ++ parent_offset, uid++, NULL, 0); ++ } ++ } ++ ++ g_queue_free(list); ++ acpi_table_end(linker, &table); ++} ++ + static void acpi_dsdt_add_psd(Aml *dev, int cpus) + { + Aml *pkg; +diff --git a/hw/arm/virt.c b/hw/arm/virt.c +index 3394d3a6a6..d31675b0fd 100644 +--- a/hw/arm/virt.c ++++ b/hw/arm/virt.c +@@ -369,6 +369,39 @@ static void fdt_add_timer_nodes(const VirtMachineState *vms) + GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); + } + ++/* ++ * In CLIDR_EL1 exposed to guest by the hypervisor, L1 cache type ++ * maybe unified or seperate ins and data. We need to read the ++ * guest visable CLIDR_EL1 and check L1 cache type. ++ */ ++bool cpu_l1_cache_unified(int cpu) ++{ ++ bool unified = false; ++ uint64_t clidr; ++ ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); ++ CPUState *cs = CPU(armcpu); ++ int ret; ++ ++ if (kvm_enabled()) { ++ struct kvm_one_reg reg = { ++ .id = ARM64_REG_CLIDR_EL1, ++ .addr = (uintptr_t)&clidr ++ }; ++ ++ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); ++ if (ret) { ++ error_setg(&error_fatal, "Get vCPU clidr from KVM failed:%d", ret); ++ return unified; ++ } ++ ++ if (CLIDR_CTYPE(clidr, 1) == CTYPE_UNIFIED) { ++ unified = true; ++ } ++ } ++ ++ return unified; ++} ++ + static void fdt_add_l3cache_nodes(const VirtMachineState *vms) + { + int i; +@@ -383,9 +416,10 @@ static void fdt_add_l3cache_nodes(const VirtMachineState *vms) + qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cache"); + qemu_fdt_setprop_string(ms->fdt, nodename, "cache-unified", "true"); + qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-level", 3); +- qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-size", 0x2000000); +- qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-line-size", 128); +- qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-sets", 2048); ++ qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-size", ARM_L3CACHE_SIZE); ++ qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-line-size", ++ ARM_L3CACHE_LINE_SIZE); ++ qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-sets", ARM_L3CACHE_SETS); + qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", + qemu_fdt_alloc_phandle(ms->fdt)); + g_free(nodename); +@@ -404,10 +438,12 @@ static void fdt_add_l2cache_nodes(const VirtMachineState *vms) + char *nodename = g_strdup_printf("/cpus/l2-cache%d", cpu); + + qemu_fdt_add_subnode(ms->fdt, nodename); ++ qemu_fdt_setprop_string(ms->fdt, nodename, "cache-unified", "true"); + qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cache"); +- qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-size", 0x80000); +- qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-line-size", 64); +- qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-sets", 1024); ++ qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-size", ARM_L2CACHE_SIZE); ++ qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-line-size", ++ ARM_L2CACHE_LINE_SIZE); ++ qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-sets", ARM_L2CACHE_SETS); + qemu_fdt_setprop_phandle(ms->fdt, nodename, "next-level-cache", + next_path); + qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", +@@ -421,18 +457,32 @@ static void fdt_add_l2cache_nodes(const VirtMachineState *vms) + static void fdt_add_l1cache_prop(const VirtMachineState *vms, + char *nodename, int cpu) + { +- const MachineState *ms = MACHINE(vms); +- char *cachename = g_strdup_printf("/cpus/l2-cache%d", cpu); +- +- qemu_fdt_setprop_cell(ms->fdt, nodename, "d-cache-size", 0x10000); +- qemu_fdt_setprop_cell(ms->fdt, nodename, "d-cache-line-size", 64); +- qemu_fdt_setprop_cell(ms->fdt, nodename, "d-cache-sets", 256); +- qemu_fdt_setprop_cell(ms->fdt, nodename, "i-cache-size", 0x10000); +- qemu_fdt_setprop_cell(ms->fdt, nodename, "i-cache-line-size", 64); +- qemu_fdt_setprop_cell(ms->fdt, nodename, "i-cache-sets", 256); +- qemu_fdt_setprop_phandle(ms->fdt, nodename, "next-level-cache", +- cachename); +- g_free(cachename); ++ const MachineState *ms = MACHINE(vms); ++ char *next_path = g_strdup_printf("/cpus/l2-cache%d", cpu); ++ bool unified_l1 = cpu_l1_cache_unified(0); ++ ++ if (unified_l1) { ++ qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-size", ARM_L1CACHE_SIZE); ++ qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-line-size", ++ ARM_L1CACHE_LINE_SIZE); ++ qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-sets", ARM_L1CACHE_SETS); ++ } else { ++ qemu_fdt_setprop_cell(ms->fdt, nodename, "d-cache-size", ++ ARM_L1DCACHE_SIZE); ++ qemu_fdt_setprop_cell(ms->fdt, nodename, "d-cache-line-size", ++ ARM_L1DCACHE_LINE_SIZE); ++ qemu_fdt_setprop_cell(ms->fdt, nodename, "d-cache-sets", ++ ARM_L1DCACHE_SETS); ++ qemu_fdt_setprop_cell(ms->fdt, nodename, "i-cache-size", ++ ARM_L1ICACHE_SIZE); ++ qemu_fdt_setprop_cell(ms->fdt, nodename, "i-cache-line-size", ++ ARM_L1ICACHE_LINE_SIZE); ++ qemu_fdt_setprop_cell(ms->fdt, nodename, "i-cache-sets", ++ ARM_L1ICACHE_SETS); ++ } ++ qemu_fdt_setprop_phandle(ms->fdt, nodename, "next-level-cache", next_path); ++ ++ g_free(next_path); + } + + static void fdt_add_cpu_nodes(const VirtMachineState *vms) +diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h +index 5e9b72c024..84a72267f9 100644 +--- a/include/hw/acpi/aml-build.h ++++ b/include/hw/acpi/aml-build.h +@@ -221,49 +221,6 @@ struct AcpiBuildTables { + BIOSLinker *linker; + } AcpiBuildTables; + +-/* Definitions of the hardcoded cache info*/ +-typedef enum { +- ARM_L1D_CACHE, +- ARM_L1I_CACHE, +- ARM_L2_CACHE, +- ARM_L3_CACHE +-} ArmCacheType; +- +-/* L1 data cache: */ +-#define ARM_L1DCACHE_SIZE 65536 +-#define ARM_L1DCACHE_SETS 256 +-#define ARM_L1DCACHE_ASSOCIATIVITY 4 +-#define ARM_L1DCACHE_ATTRIBUTES 2 +-#define ARM_L1DCACHE_LINE_SIZE 64 +- +-/* L1 instruction cache: */ +-#define ARM_L1ICACHE_SIZE 65536 +-#define ARM_L1ICACHE_SETS 256 +-#define ARM_L1ICACHE_ASSOCIATIVITY 4 +-#define ARM_L1ICACHE_ATTRIBUTES 4 +-#define ARM_L1ICACHE_LINE_SIZE 64 +- +-/* Level 2 unified cache: */ +-#define ARM_L2CACHE_SIZE 524288 +-#define ARM_L2CACHE_SETS 1024 +-#define ARM_L2CACHE_ASSOCIATIVITY 8 +-#define ARM_L2CACHE_ATTRIBUTES 10 +-#define ARM_L2CACHE_LINE_SIZE 64 +- +-/* Level 3 unified cache: */ +-#define ARM_L3CACHE_SIZE 33554432 +-#define ARM_L3CACHE_SETS 2048 +-#define ARM_L3CACHE_ASSOCIATIVITY 15 +-#define ARM_L3CACHE_ATTRIBUTES 10 +-#define ARM_L3CACHE_LINE_SIZE 128 +- +-struct offset_status { +- uint32_t parent; +- uint32_t l2_offset; +- uint32_t l1d_offset; +- uint32_t l1i_offset; +-}; +- + typedef + struct CrsRangeEntry { + uint64_t base; +@@ -458,6 +415,7 @@ Aml *aml_sizeof(Aml *arg); + Aml *aml_concatenate(Aml *source1, Aml *source2, Aml *target); + Aml *aml_object_type(Aml *object); + ++void build_append_byte(GArray *array, uint8_t val); + void build_append_int_noprefix(GArray *table, uint64_t value, int size); + + typedef struct AcpiTable { +@@ -535,10 +493,12 @@ void build_srat_memory(GArray *table_data, uint64_t base, + void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms, + const char *oem_id, const char *oem_table_id); + +-void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, +- const char *oem_id, const char *oem_table_id); ++void build_processor_hierarchy_node(GArray *tbl, uint32_t flags, ++ uint32_t parent, uint32_t id, ++ uint32_t *priv_rsrc, ++ uint32_t priv_num); + +-void build_pptt_arm(GArray *table_data, BIOSLinker *linker, MachineState *ms, ++void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, + const char *oem_id, const char *oem_table_id); + + void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f, +diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h +index 3fc1adcb42..7b99e84377 100644 +--- a/include/hw/arm/virt.h ++++ b/include/hw/arm/virt.h +@@ -58,6 +58,65 @@ + /* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */ + #define PVTIME_SIZE_PER_CPU 64 + ++/* ARM CLIDR_EL1 related definitions */ ++/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */ ++#define CTYPE_NONE 0b000 ++#define CTYPE_INS 0b001 ++#define CTYPE_DATA 0b010 ++#define CTYPE_INS_DATA 0b011 ++#define CTYPE_UNIFIED 0b100 ++ ++#define ARM64_REG_CLIDR_EL1 ARM64_SYS_REG(3, 1, 0, 0, 1) ++ ++#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) ++#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) ++#define CLIDR_CTYPE(clidr, level) \ ++ (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) ++ ++/* L1 data cache */ ++#define ARM_L1DCACHE_SIZE 65536 ++#define ARM_L1DCACHE_SETS 256 ++#define ARM_L1DCACHE_ASSOCIATIVITY 4 ++#define ARM_L1DCACHE_ATTRIBUTES 2 ++#define ARM_L1DCACHE_LINE_SIZE 64 ++ ++/* L1 instruction cache */ ++#define ARM_L1ICACHE_SIZE 65536 ++#define ARM_L1ICACHE_SETS 256 ++#define ARM_L1ICACHE_ASSOCIATIVITY 4 ++#define ARM_L1ICACHE_ATTRIBUTES 4 ++#define ARM_L1ICACHE_LINE_SIZE 64 ++ ++/* L1 unified cache */ ++#define ARM_L1CACHE_SIZE 131072 ++#define ARM_L1CACHE_SETS 256 ++#define ARM_L1CACHE_ASSOCIATIVITY 4 ++#define ARM_L1CACHE_ATTRIBUTES 10 ++#define ARM_L1CACHE_LINE_SIZE 128 ++ ++/* L2 unified cache */ ++#define ARM_L2CACHE_SIZE 524288 ++#define ARM_L2CACHE_SETS 1024 ++#define ARM_L2CACHE_ASSOCIATIVITY 8 ++#define ARM_L2CACHE_ATTRIBUTES 10 ++#define ARM_L2CACHE_LINE_SIZE 64 ++ ++/* L3 unified cache */ ++#define ARM_L3CACHE_SIZE 33554432 ++#define ARM_L3CACHE_SETS 2048 ++#define ARM_L3CACHE_ASSOCIATIVITY 15 ++#define ARM_L3CACHE_ATTRIBUTES 10 ++#define ARM_L3CACHE_LINE_SIZE 128 ++ ++/* Definitions of the hardcoded cache info */ ++typedef enum { ++ ARM_L1D_CACHE, ++ ARM_L1I_CACHE, ++ ARM_L1_CACHE, ++ ARM_L2_CACHE, ++ ARM_L3_CACHE ++} ArmCacheType; ++ + enum { + VIRT_FLASH, + VIRT_MEM, +@@ -191,6 +250,7 @@ void virt_madt_cpu_entry(AcpiDeviceIf *adev, int uid, + bool force_enabled); + void virt_acpi_dsdt_cpu_cppc(AcpiDeviceIf *adev, int uid, + int num_cpu, Aml *dev); ++bool cpu_l1_cache_unified(int cpu); + + /* Return the number of used redistributor regions */ + static inline int virt_gicv3_redist_region_count(VirtMachineState *vms) +-- +2.41.0.windows.1 + diff --git a/hw-mips-Build-fw_cfg.c-once.patch b/hw-mips-Build-fw_cfg.c-once.patch new file mode 100644 index 0000000..b8333fa --- /dev/null +++ b/hw-mips-Build-fw_cfg.c-once.patch @@ -0,0 +1,37 @@ +From 9fd0695c0158250a0d9a8ab6fb88cb8d030f5b9f Mon Sep 17 00:00:00 2001 +From: guping +Date: Tue, 8 Oct 2024 01:44:34 +0000 +Subject: [PATCH] hw/mips: Build fw_cfg.c once cherry-pick from + f2a9c31dbba2976796c0391dc7426238e798c644 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Nothing in fw_cfg.c requires target-specific knowledge, +build it once for the 4 MIPS variants. + +Signed-off-by: default avatarPhilippe Mathieu-Daudé +Reviewed-by: Thomas Huth's avatarThomas Huth +Reviewed-by: default avatarMichael Tokarev +Signed-off-by: default avatarMichael Tokarev + +Signed-off-by: guping +--- + hw/mips/meson.build | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/hw/mips/meson.build b/hw/mips/meson.build +index dd0101ad4d..1e57c63374 100644 +--- a/hw/mips/meson.build ++++ b/hw/mips/meson.build +@@ -1,6 +1,6 @@ + mips_ss = ss.source_set() + mips_ss.add(files('bootloader.c', 'mips_int.c')) +-mips_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c')) ++common_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c')) + mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c', 'loongson3_virt.c')) + mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c')) + mips_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('cps.c')) +-- +2.41.0.windows.1 + diff --git a/minikconf-print-error-entirely-on-stderr.patch b/minikconf-print-error-entirely-on-stderr.patch new file mode 100644 index 0000000..bc99f96 --- /dev/null +++ b/minikconf-print-error-entirely-on-stderr.patch @@ -0,0 +1,38 @@ +From f95f7e74c6b8e656a3217508706db8c7f3c84e6d Mon Sep 17 00:00:00 2001 +From: guping +Date: Tue, 8 Oct 2024 01:21:07 +0000 +Subject: [PATCH] minikconf: print error entirely on stderr cherry-pick from + f9423e9f0ad14b186c65d6eb207438d2eddd24ea +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +While debugging an invalid configuration, I noticed that the clauses debug +ends up on stderr but the header ("The following clauses were found..." +ends up on stdout. This makes the contents of meson-logs/meson-log.txt +a bit confusing. + +Reviewed-by: default avatarPhilippe Mathieu-Daudé +Signed-off-by: default avatarPaolo Bonzini + +Signed-off-by: guping +--- + scripts/minikconf.py | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/scripts/minikconf.py b/scripts/minikconf.py +index bcd91015d3..6f7f43b291 100644 +--- a/scripts/minikconf.py ++++ b/scripts/minikconf.py +@@ -112,7 +112,7 @@ def has_value(self): + def set_value(self, val, clause): + self.clauses_for_var.append(clause) + if self.has_value() and self.value != val: +- print("The following clauses were found for " + self.name) ++ print("The following clauses were found for " + self.name, file=sys.stderr) + for i in self.clauses_for_var: + print(" " + str(i), file=sys.stderr) + raise KconfigDataError('contradiction between clauses when setting %s' % self) +-- +2.41.0.windows.1 + diff --git a/pc-bios-keymaps-Use-the-official-xkb-name-for-Arabic.patch b/pc-bios-keymaps-Use-the-official-xkb-name-for-Arabic.patch new file mode 100644 index 0000000..83cd166 --- /dev/null +++ b/pc-bios-keymaps-Use-the-official-xkb-name-for-Arabic.patch @@ -0,0 +1,61 @@ +From e0af5020f882bb9152afa50c6e24a93019946e75 Mon Sep 17 00:00:00 2001 +From: Peter Maydell +Date: Tue, 20 Jun 2023 17:20:24 +0100 +Subject: [PATCH] pc-bios/keymaps: Use the official xkb name for Arabic layout, + not the legacy synonym +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The xkb official name for the Arabic keyboard layout is 'ara'. +However xkb has for at least the past 15 years also permitted it to +be named via the legacy synonym 'ar'. In xkeyboard-config 2.39 this +synoynm was removed, which breaks compilation of QEMU: + +FAILED: pc-bios/keymaps/ar +/home/fred/qemu-git/src/qemu/build-full/qemu-keymap -f pc-bios/keymaps/ar -l ar +xkbcommon: ERROR: Couldn't find file "symbols/ar" in include paths +xkbcommon: ERROR: 1 include paths searched: +xkbcommon: ERROR: /usr/share/X11/xkb +xkbcommon: ERROR: 3 include paths could not be added: +xkbcommon: ERROR: /home/fred/.config/xkb +xkbcommon: ERROR: /home/fred/.xkb +xkbcommon: ERROR: /etc/xkb +xkbcommon: ERROR: Abandoning symbols file "(unnamed)" +xkbcommon: ERROR: Failed to compile xkb_symbols +xkbcommon: ERROR: Failed to compile keymap + +The upstream xkeyboard-config change removing the compat +mapping is: +https://gitlab.freedesktop.org/xkeyboard-config/xkeyboard-config/-/commit/470ad2cd8fea84d7210377161d86b31999bb5ea6 + +Make QEMU always ask for the 'ara' xkb layout, which should work on +both older and newer xkeyboard-config. We leave the QEMU name for +this keyboard layout as 'ar'; it is not the only one where our name +for it deviates from the xkb standard name. + +Cc: qemu-stable@nongnu.org +Signed-off-by: Peter Maydell +Reviewed-by: Richard Henderson +Reviewed-by: Philippe Mathieu-Daudé +Reviewed-by: Daniel P. Berrangé +Message-id: 20230620162024.1132013-1-peter.maydell@linaro.org +Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1709 +--- + pc-bios/keymaps/meson.build | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/pc-bios/keymaps/meson.build b/pc-bios/keymaps/meson.build +index 44247a12b5..6e025cddf2 100644 +--- a/pc-bios/keymaps/meson.build ++++ b/pc-bios/keymaps/meson.build +@@ -1,5 +1,5 @@ + keymaps = { +- 'ar': '-l ar', ++ 'ar': '-l ara', + 'bepo': '-l fr -v dvorak', + 'cz': '-l cz', + 'da': '-l dk', +-- +2.41.0.windows.1 + diff --git a/qemu.spec b/qemu.spec index 07c8cda..d0267e0 100644 --- a/qemu.spec +++ b/qemu.spec @@ -3,7 +3,7 @@ Name: qemu Version: 6.2.0 -Release: 101 +Release: 102 Epoch: 10 Summary: QEMU is a generic and open source machine emulator and virtualizer License: GPLv2 and BSD and MIT and CC-BY-SA-4.0 @@ -1070,6 +1070,12 @@ Patch1055: hw-i386-vmmouse-Require-i8042-property-to-be-set.patch Patch1056: vhost-backend-avoid-overflow-on-memslots_limit.patch Patch1057: sysemu-Cleanup-qemu_run_machine_init_done_notifiers.patch Patch1058: python-aqmp-use-absolute-import-statement.patch +Patch1059: pc-bios-keymaps-Use-the-official-xkb-name-for-Arabic.patch +Patch1060: hw-arm-virt-Keep-Guest-L1-cache-type-consistent-with.patch +Patch1061: target-ppc-Remove-extra-space-from-s128-field-in-ppc.patch +Patch1062: minikconf-print-error-entirely-on-stderr.patch +Patch1063: hw-mips-Build-fw_cfg.c-once.patch +Patch1064: target-ppc-Remove-unused-xer_-macros.patch BuildRequires: flex BuildRequires: gcc @@ -1668,6 +1674,14 @@ getent passwd qemu >/dev/null || \ %endif %changelog +* Sat Nov 30 2024 - 10:6.2.0-102 +- target/ppc: Remove unused xer_* macros +- hw/mips: Build fw_cfg.c once +- minikconf: print error entirely on stderr +- target/ppc: Remove extra space from s128 field in ppc_vsr_t +- hw/arm/virt:Keep Guest L1 cache type consistent with KVM +- pc-bios/keymaps: Use the official xkb name for Arabic layout, not the legacy synonym + * Mon Oct 21 2024 - 10:6.2.0-101 - python/aqmp: use absolute import statement - sysemu: Cleanup qemu_run_machine_init_done_notifiers() diff --git a/target-ppc-Remove-extra-space-from-s128-field-in-ppc.patch b/target-ppc-Remove-extra-space-from-s128-field-in-ppc.patch new file mode 100644 index 0000000..5f21fa0 --- /dev/null +++ b/target-ppc-Remove-extra-space-from-s128-field-in-ppc.patch @@ -0,0 +1,37 @@ +From 21b17f03d4c506a8baca9d96f33e275bffec752f Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=E5=88=98=E5=A9=A720201110?= + +Date: Sun, 29 Sep 2024 16:52:32 +0800 +Subject: [PATCH] target/ppc: Remove extra space from s128 field in ppc_vsr_t +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Very trivial rogue space removal. There are two spaces between Int128 +and s128 in ppc_vsr_t struct, where it should be only one. + +Signed-off-by: Víctor Colombo +Reviewed-by: Daniel Henrique Barboza +Message-Id: <20220906125523.38765-2-victor.colombo@eldorado.org.br> +Signed-off-by: Daniel Henrique Barboza +Signed-off-by: Liu Jing +--- + target/ppc/cpu.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h +index 1281323c02..8e924c6273 100644 +--- a/target/ppc/cpu.h ++++ b/target/ppc/cpu.h +@@ -231,7 +231,7 @@ typedef union _ppc_vsr_t { + #ifdef CONFIG_INT128 + __uint128_t u128; + #endif +- Int128 s128; ++ Int128 s128; + } ppc_vsr_t; + + typedef ppc_vsr_t ppc_avr_t; +-- +2.41.0.windows.1 + diff --git a/target-ppc-Remove-unused-xer_-macros.patch b/target-ppc-Remove-unused-xer_-macros.patch new file mode 100644 index 0000000..f3f4ba7 --- /dev/null +++ b/target-ppc-Remove-unused-xer_-macros.patch @@ -0,0 +1,39 @@ +From fe8e83c0695b8215a3eab44eb4e40e4c4b90b2d8 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=E5=88=98=E5=A9=A720201110?= + +Date: Sun, 29 Sep 2024 17:25:23 +0800 +Subject: [PATCH] target/ppc: Remove unused xer_* macros +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The macros xer_ov, xer_ca, xer_ov32, and xer_ca32 are both unused and +hiding the usage of env. Remove them. + +Signed-off-by: Víctor Colombo +Reviewed-by: Daniel Henrique Barboza +Message-Id: <20220906125523.38765-3-victor.colombo@eldorado.org.br> +Signed-off-by: Daniel Henrique Barboza +Signed-off-by: Liu Jing +--- + target/ppc/cpu.h | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h +index 1281323c02..3c2210096d 100644 +--- a/target/ppc/cpu.h ++++ b/target/ppc/cpu.h +@@ -1448,10 +1448,6 @@ typedef PowerPCCPU ArchCPU; + #define XER_CMP 8 + #define XER_BC 0 + #define xer_so (env->so) +-#define xer_ov (env->ov) +-#define xer_ca (env->ca) +-#define xer_ov32 (env->ov) +-#define xer_ca32 (env->ca) + #define xer_cmp ((env->xer >> XER_CMP) & 0xFF) + #define xer_bc ((env->xer >> XER_BC) & 0x7F) + +-- +2.41.0.windows.1 +