From 82293e21ded10ebdbd0efae9f9ef090f1fc62705 Mon Sep 17 00:00:00 2001 From: Liu Jing Date: Mon, 21 Oct 2024 19:15:42 +0800 Subject: [PATCH] target/m68k: Fix MACSR to CCR First, we were writing to the entire SR register, instead of only the flags portion. Second, we were not clearing C as per the documentation (X was cleared via the 0xf mask). Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier Message-Id: <20220913142818.7802-2-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier Signed-off-by: Liu Jing --- target/m68k/translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index af43c8eab8..657f663fbe 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -5809,8 +5809,10 @@ DISAS_INSN(from_mext) DISAS_INSN(macsr_to_ccr) { TCGv tmp = tcg_temp_new(); - tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf); - gen_helper_set_sr(cpu_env, tmp); + + /* Note that X and C are always cleared. */ + tcg_gen_andi_i32(tmp, QREG_MACSR, CCF_N | CCF_Z | CCF_V); + gen_helper_set_ccr(cpu_env, tmp); tcg_temp_free(tmp); set_cc_op(s, CC_OP_FLAGS); } -- 2.41.0.windows.1