401984bbd1
- target/i386: Add EPYC-Genoa model to support Zen 4 processor series - target/i386: Add VNMI and automatic IBRS feature bits - target/i386: Add missing feature bits in EPYC-Milan model - target/i386: Add feature bits for CPUID_Fn80000021_EAX - target/i386: Add a couple of feature bits in 8000_0008_EBX - target/i386: Add new EPYC CPU versions with updated cache_info - target/i386: allow versioned CPUs to specify new cache_info Signed-off-by: AlexChen <alex.chen@huawei.com> (cherry picked from commit 941be8259b4a01d66f0c9c9d16c7acf8933688eb)
99 lines
4.0 KiB
Diff
99 lines
4.0 KiB
Diff
From bb5ec050bb8144c464cfe1b0954230ea2d5b4803 Mon Sep 17 00:00:00 2001
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From: Babu Moger <babu.moger@amd.com>
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Date: Thu, 4 May 2023 15:53:11 -0500
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Subject: [PATCH] target/i386: Add VNMI and automatic IBRS feature bits
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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mainline inclusion
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from mainline-8.1.0
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commit 62a798d4bc2c3e767d94670776c77a7df274d7c5
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category: feature
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bugzilla: https://gitee.com/openeuler/qemu/issues/IAUSKJ
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Reference: https://gitlab.com/qemu-project/qemu/-/commit/62a798d4bc2c3e767d94670776c77a7df274d7c5
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commit 62a798d4bc2c3e767d94670776c77a7df274d7c5 upstream
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Add the following featute bits.
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vnmi: Virtual NMI (VNMI) allows the hypervisor to inject the NMI into the
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guest without using Event Injection mechanism meaning not required to
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track the guest NMI and intercepting the IRET.
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The presence of this feature is indicated via the CPUID function
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0x8000000A_EDX[25].
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automatic-ibrs :
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The AMD Zen4 core supports a new feature called Automatic IBRS.
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It is a "set-and-forget" feature that means that, unlike e.g.,
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s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation
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resources automatically across CPL transitions.
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The presence of this feature is indicated via the CPUID function
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0x80000021_EAX[8].
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The documention for the features are available in the links below.
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a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
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Revision B1 Processors
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b. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision
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40332 4.05 Date October 2022
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Signed-off-by: Santosh Shukla <santosh.shukla@amd.com>
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Signed-off-by: Kim Phillips <kim.phillips@amd.com>
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Signed-off-by: Babu Moger <babu.moger@amd.com>
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Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
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Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf
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Message-Id: <20230504205313.225073-7-babu.moger@amd.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 62a798d4bc2c3e767d94670776c77a7df274d7c5)
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---
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target/i386/cpu.c | 4 ++--
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target/i386/cpu.h | 3 +++
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2 files changed, 5 insertions(+), 2 deletions(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 4d7f948eb1..59b585b0d0 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -806,7 +806,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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"pfthreshold", "avic", NULL, "v-vmsave-vmload",
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"vgif", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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- NULL, NULL, NULL, NULL,
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+ NULL, "vnmi", NULL, NULL,
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"svme-addr-chk", NULL, NULL, NULL,
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},
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.cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
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@@ -963,7 +963,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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.feat_names = {
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"no-nested-data-bp", NULL, "lfence-always-serializing", NULL,
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NULL, NULL, "null-sel-clr-base", NULL,
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- NULL, NULL, NULL, NULL,
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+ "auto-ibrs", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 7b1190c3f2..84910db8bb 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -760,6 +760,7 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
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#define CPUID_SVM_AVIC (1U << 13)
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#define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15)
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#define CPUID_SVM_VGIF (1U << 16)
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+#define CPUID_SVM_VNMI (1U << 25)
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#define CPUID_SVM_SVME_ADDR_CHK (1U << 28)
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/* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
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@@ -948,6 +949,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
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#define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2)
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/* Null Selector Clears Base */
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#define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6)
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+/* Automatic IBRS */
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+#define CPUID_8000_0021_EAX_AUTO_IBRS (1U << 8)
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#define CPUID_XSAVE_XSAVEOPT (1U << 0)
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#define CPUID_XSAVE_XSAVEC (1U << 1)
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--
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2.45.1.windows.1
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