qemu/target-i386-correctly-mask-SSE4a-bit-indices-in-regi.patch
Jiabo Feng 11aadaf893 QEMU update to version 6.2.0-101:
- python/aqmp: use absolute import statement
- sysemu: Cleanup qemu_run_machine_init_done_notifiers()
- vhost-backend: avoid overflow on memslots_limit
- hw/i386/vmmouse: Require 'i8042' property to be set
- hw/scsi/megasas: Fails command if SGL buffer overflows
- target/i386/kvm: Replace use of __u32 type
- hw/avr: Realize AVRCPU qdev object using qdev_realize()
- qemu-keymap: Add license in generated files
- configure: Symlink binaries using .exe suffix with MinGW
- ui: remove break after g_assert_not_reached()
- io/channel-websock: Replace strlen(const_str) by sizeof(const_str) - 1
- target/ppc: Add HASHKEYR and HASHPKEYR SPRs
- tests: Fix error strings
- Hexagon (target/hexagon) remove unused encodings
- target/i386: introduce insn_get_addr
- target/i386: REPZ and REPNZ are mutually exclusive
- target/i386: correctly mask SSE4a bit indices in register operands
- bios-tables-test: Make oem-fields tests be consistent
- tests/vm: update NetBSD to 9.3
- monitor/hmp-cmds: Avoid displaying bogus size in 'info pci' When BAR aren't mapped, we get:
- virtio-mem: don't warn about THP sizes on a kernel without THP Support
- Subject: [PATCH] kvm: Use 'unsigned long' for request argument in functions  wrapping ioctl()

Signed-off-by: Jiabo Feng <fengjiabo1@huawei.com>
(cherry picked from commit 2430c96ac522f910c11eb98c2d9f74c2c3336a00)
2024-10-21 11:02:49 +08:00

44 lines
1.7 KiB
Diff

From 4d18374e62d3206d564d9a6a7154e7eb4b48ecb2 Mon Sep 17 00:00:00 2001
From: liujing <liujing_yewu@cmss.chinamobile.com>
Date: Wed, 18 Sep 2024 16:44:18 +0800
Subject: [PATCH] target/i386: correctly mask SSE4a bit indices in register
operands
SSE4a instructions EXTRQ and INSERTQ have two bit index operands, that can be
immediates or taken from an XMM register. In both cases, the fields are
6-bit wide and the top two bits in the byte are ignored. translate.c is
doing that correctly for the immediate case, but not for the XMM case, so
fix it.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Liu Jing <liujing_yewu@cmss.chinamobile.com>
---
target/i386/ops_sse.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index 6f1fc174b3..898b7e4292 100644
--- a/target/i386/ops_sse.h
+++ b/target/i386/ops_sse.h
@@ -899,7 +899,7 @@ static inline uint64_t helper_extrq(uint64_t src, int shift, int len)
void helper_extrq_r(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{
- d->ZMM_Q(0) = helper_extrq(d->ZMM_Q(0), s->ZMM_B(1), s->ZMM_B(0));
+ d->ZMM_Q(0) = helper_extrq(d->ZMM_Q(0), s->ZMM_B(1) & 63, s->ZMM_B(0) & 63);
}
void helper_extrq_i(CPUX86State *env, ZMMReg *d, int index, int length)
@@ -921,7 +921,7 @@ static inline uint64_t helper_insertq(uint64_t src, int shift, int len)
void helper_insertq_r(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{
- d->ZMM_Q(0) = helper_insertq(s->ZMM_Q(0), s->ZMM_B(9), s->ZMM_B(8));
+ d->ZMM_Q(0) = helper_insertq(s->ZMM_Q(0), s->ZMM_B(9) & 63, s->ZMM_B(8) & 63);
}
void helper_insertq_i(CPUX86State *env, ZMMReg *d, int index, int length)
--
2.41.0.windows.1