401984bbd1
- target/i386: Add EPYC-Genoa model to support Zen 4 processor series - target/i386: Add VNMI and automatic IBRS feature bits - target/i386: Add missing feature bits in EPYC-Milan model - target/i386: Add feature bits for CPUID_Fn80000021_EAX - target/i386: Add a couple of feature bits in 8000_0008_EBX - target/i386: Add new EPYC CPU versions with updated cache_info - target/i386: allow versioned CPUs to specify new cache_info Signed-off-by: AlexChen <alex.chen@huawei.com> (cherry picked from commit 941be8259b4a01d66f0c9c9d16c7acf8933688eb)
145 lines
5.0 KiB
Diff
145 lines
5.0 KiB
Diff
From e5e589d3b9023861474e53428e721482614cee6d Mon Sep 17 00:00:00 2001
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From: Babu Moger <babu.moger@amd.com>
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Date: Thu, 4 May 2023 15:53:10 -0500
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Subject: [PATCH] target/i386: Add missing feature bits in EPYC-Milan model
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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mainline inclusion
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from mainline-8.1.0
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commit 27f03be6f59d04bd5673ba1e1628b2b490f9a9ff
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category: feature
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bugzilla: https://gitee.com/openeuler/qemu/issues/IAUSKJ
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Reference: https://gitlab.com/qemu-project/qemu/-/commit/27f03be6f59d04bd5673ba1e1628b2b490f9a9ff
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commit 27f03be6f59d04bd5673ba1e1628b2b490f9a9ff upstream
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Add the following feature bits for EPYC-Milan model and bump the version.
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vaes : Vector VAES(ENC|DEC), VAES(ENC|DEC)LAST instruction support
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vpclmulqdq : Vector VPCLMULQDQ instruction support
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stibp-always-on : Single Thread Indirect Branch Prediction Mode has enhanced
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performance and may be left Always on
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amd-psfd : Predictive Store Forward Disable
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no-nested-data-bp : Processor ignores nested data breakpoints
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lfence-always-serializing : LFENCE instruction is always serializing
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null-sel-clr-base : Null Selector Clears Base. When this bit is
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set, a null segment load clears the segment base
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These new features will be added in EPYC-Milan-v2. The "-cpu help" output
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after the change will be.
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x86 EPYC-Milan (alias configured by machine type)
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x86 EPYC-Milan-v1 AMD EPYC-Milan Processor
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x86 EPYC-Milan-v2 AMD EPYC-Milan Processor
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The documentation for the features are available in the links below.
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a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
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Revision B1 Processors
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b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING
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c. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision
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40332 4.05 Date October 2022
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Signed-off-by: Babu Moger <babu.moger@amd.com>
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Acked-by: Michael S. Tsirkin <mst@redhat.com>
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Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
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Link: https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf
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Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf
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Message-Id: <20230504205313.225073-6-babu.moger@amd.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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---
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target/i386/cpu.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 70 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 527135ca9d..4d7f948eb1 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -1949,6 +1949,56 @@ static const CPUCaches epyc_milan_cache_info = {
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},
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};
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+static const CPUCaches epyc_milan_v2_cache_info = {
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+ .l1d_cache = &(CPUCacheInfo) {
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+ .type = DATA_CACHE,
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+ .level = 1,
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+ .size = 32 * KiB,
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+ .line_size = 64,
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+ .associativity = 8,
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+ .partitions = 1,
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+ .sets = 64,
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+ .lines_per_tag = 1,
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+ .self_init = 1,
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+ .no_invd_sharing = true,
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+ },
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+ .l1i_cache = &(CPUCacheInfo) {
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+ .type = INSTRUCTION_CACHE,
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+ .level = 1,
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+ .size = 32 * KiB,
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+ .line_size = 64,
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+ .associativity = 8,
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+ .partitions = 1,
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+ .sets = 64,
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+ .lines_per_tag = 1,
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+ .self_init = 1,
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+ .no_invd_sharing = true,
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+ },
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+ .l2_cache = &(CPUCacheInfo) {
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+ .type = UNIFIED_CACHE,
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+ .level = 2,
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+ .size = 512 * KiB,
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+ .line_size = 64,
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+ .associativity = 8,
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+ .partitions = 1,
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+ .sets = 1024,
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+ .lines_per_tag = 1,
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+ },
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+ .l3_cache = &(CPUCacheInfo) {
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+ .type = UNIFIED_CACHE,
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+ .level = 3,
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+ .size = 32 * MiB,
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+ .line_size = 64,
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+ .associativity = 16,
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+ .partitions = 1,
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+ .sets = 32768,
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+ .lines_per_tag = 1,
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+ .self_init = true,
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+ .inclusive = true,
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+ .complex_indexing = false,
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+ },
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+};
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+
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/* The following VMX features are not supported by KVM and are left out in the
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* CPU definitions:
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*
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@@ -4833,6 +4883,26 @@ static const X86CPUDefinition builtin_x86_defs[] = {
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.xlevel = 0x8000001E,
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.model_id = "AMD EPYC-Milan Processor",
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.cache_info = &epyc_milan_cache_info,
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+ .versions = (X86CPUVersionDefinition[]) {
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+ { .version = 1 },
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+ {
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+ .version = 2,
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+ .props = (PropValue[]) {
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+ { "model-id",
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+ "AMD EPYC-Milan-v2 Processor" },
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+ { "vaes", "on" },
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+ { "vpclmulqdq", "on" },
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+ { "stibp-always-on", "on" },
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+ { "amd-psfd", "on" },
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+ { "no-nested-data-bp", "on" },
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+ { "lfence-always-serializing", "on" },
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+ { "null-sel-clr-base", "on" },
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+ { /* end of list */ }
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+ },
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+ .cache_info = &epyc_milan_v2_cache_info
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+ },
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+ { /* end of list */ }
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+ }
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},
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};
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--
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2.45.1.windows.1
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