7bb77ea74f
- Introduce the SM4 cipher algorithms (OSCCA GB/T 32907-2016).
- intel_iommu: Add missed sanity check for 256-bit invalidation queue
- linux-user: use 'max' instead of 'qemu32' / 'qemu64' by default
- chardev/baum: Use definitions to avoid dynamic stack allocation
- ui/console: Get tab completion working again in the SDL monitor vc
- s390x/tcg: Fix opcode for lzrf
- virtiofsd: use g_date_time_get_microsecond to get subsecond
- ui/curses: Avoid dynamic stack allocation
- target/m68k: always call gen_exit_tb() after writes to SR
- target/m68k: Perform writback before modifying SR
- target/m68k: Fix MACSR to CCR
- target/m68k: Implement atomic test-and-set
- block/nvme: nvme_process_completion() fix bound for cid
- hw/pci-host: pnv_phb{3, 4}: Fix heap out-of-bound access failure
- target/ppc: Zero second doubleword of VSR registers for FPR insns
- target/ppc: Set OV32 when OV is set
- target/ppc: Zero second doubleword for VSX madd instructions
- target/ppc: Set result to QNaN for DENBCD when VXCVI occurs
- hw/pci: Add parenthesis to PCI_BUILD_BDF macro
- intel_iommu: Send IQE event when setting reserved bit in IQT_TAIL
- acpi: cpuhp: fix guest-visible maximum access size to the legacy reg block
- acpi: ged: Add macro for acpi sleep control register
- hw/pci-bridge: Add a Kconfig switch for the normal PCI bridge
- ui/vnc: fix handling of VNC_FEATURE_XVP
- s390/sclp: fix SCLP facility map
- docs/tools/qemu-img.rst: fix typo (sumarizes)
- chardev/char: fix qemu_chr_is_busy() check
- edu: fix DMA range upper bound check
- platform-bus: fix refcount leak
- hw/net/virtio-net: fix qemu set used ring flag even vhost started
- hw/net/can/sja1000: fix bug for single acceptance filter and standard frame
- tests/avocado: fix typo in replay_linux
- util/userfaultfd: Remove unused uffd_poll_events
- hw/core/ptimer: fix timer zero period condition for freq > 1GHz
- hcd-ohci: Drop ohci_service_iso_td() if ed->head & OHCI_DPTR_MASK is zero
- tests/unit/test-vmstate: Avoid dynamic stack allocation
- hw/usb/hcd-ohci: Use definition to avoid dynamic stack allocation
- hw/i386/multiboot: Avoid dynamic stack allocation
- hw/ppc/spapr: Fix code style problems reported by checkpatch
- chardev/baum: Replace magic values by X_MAX / Y_MAX definitions
- hw/intc/xics: Avoid dynamic stack allocation
- hw/net/e1000e_core: Use definition to avoid dynamic stack allocation
- intel_iommu: Fix invalidation descriptor type field
- configs: Fix typo in the sh4-softmmu devices config file
Signed-off-by: Jiabo Feng <fengjiabo1@huawei.com>
(cherry picked from commit 9813ed21ec2499c50cb58ac5fb114a1641708eb2)
48 lines
1.8 KiB
Diff
48 lines
1.8 KiB
Diff
From bdaf1aecc24fcb74424b00f2fcfe28992aa2e30a Mon Sep 17 00:00:00 2001
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From: Liu Jing <liujing_yewu@cmss.chinamobile.com>
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Date: Mon, 14 Oct 2024 16:14:28 +0800
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Subject: [PATCH] target/ppc: Zero second doubleword of VSR registers for FPR
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insns
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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FPR register are mapped to the first doubleword of the VSR registers.
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Since PowerISA v3.1, the second doubleword of the target register
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must be zeroed for FP instructions.
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This patch does it by writting 0 to the second dw everytime the
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first dw is being written using set_fpr.
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Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
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Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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Message-Id: <20220906125523.38765-8-victor.colombo@eldorado.org.br>
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Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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Signed-off-by: Liu Jing <liujing_yewu@cmss.chinamobile.com>
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---
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target/ppc/translate.c | 8 ++++++++
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1 file changed, 8 insertions(+)
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diff --git a/target/ppc/translate.c b/target/ppc/translate.c
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index 9960df6e18..153552ab50 100644
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--- a/target/ppc/translate.c
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+++ b/target/ppc/translate.c
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@@ -7290,6 +7290,14 @@ static inline void get_fpr(TCGv_i64 dst, int regno)
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static inline void set_fpr(int regno, TCGv_i64 src)
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{
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tcg_gen_st_i64(src, cpu_env, fpr_offset(regno));
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+ /*
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+ * Before PowerISA v3.1 the result of doubleword 1 of the VSR
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+ * corresponding to the target FPR was undefined. However,
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+ * most (if not all) real hardware were setting the result to 0.
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+ * Starting at ISA v3.1, the result for doubleword 1 is now defined
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+ * to be 0.
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+ */
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+ tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false));
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}
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static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
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--
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2.41.0.windows.1
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