39 lines
1.3 KiB
Diff
39 lines
1.3 KiB
Diff
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From 82293e21ded10ebdbd0efae9f9ef090f1fc62705 Mon Sep 17 00:00:00 2001
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From: Liu Jing <liujing_yewu@cmss.chinamobile.com>
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Date: Mon, 21 Oct 2024 19:15:42 +0800
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Subject: [PATCH] target/m68k: Fix MACSR to CCR
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First, we were writing to the entire SR register, instead
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of only the flags portion. Second, we were not clearing C
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as per the documentation (X was cleared via the 0xf mask).
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Laurent Vivier <laurent@vivier.eu>
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Message-Id: <20220913142818.7802-2-richard.henderson@linaro.org>
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Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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Signed-off-by: Liu Jing <liujing_yewu@cmss.chinamobile.com>
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---
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target/m68k/translate.c | 6 ++++--
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1 file changed, 4 insertions(+), 2 deletions(-)
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diff --git a/target/m68k/translate.c b/target/m68k/translate.c
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index af43c8eab8..657f663fbe 100644
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--- a/target/m68k/translate.c
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+++ b/target/m68k/translate.c
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@@ -5809,8 +5809,10 @@ DISAS_INSN(from_mext)
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DISAS_INSN(macsr_to_ccr)
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{
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TCGv tmp = tcg_temp_new();
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- tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf);
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- gen_helper_set_sr(cpu_env, tmp);
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+
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+ /* Note that X and C are always cleared. */
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+ tcg_gen_andi_i32(tmp, QREG_MACSR, CCF_N | CCF_Z | CCF_V);
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+ gen_helper_set_ccr(cpu_env, tmp);
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tcg_temp_free(tmp);
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set_cc_op(s, CC_OP_FLAGS);
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}
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--
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2.41.0.windows.1
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